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this is preliminary information on a new product now in dev elopment or undergoing evaluati on. details are subject to change without notice. november 2014 docid027190 rev 1 1/70 STGAP1S gapdrive?: galvanically isolated single gate driver datasheet - preliminary data features ? high voltage rail up to 1500 v ? driver current capability: 5 a sink/source current at 25 c ? dv/dt transient immunity 50 v/ns in full temperature range ? overall input/output propagation delay: 100 ns ? separate sink and source for easy gate driving configuration ? negative gate drive ability ? active miller clamp ? desaturation detection ? sense input ? v ce active clamping ? output 2-level turn-off ? diagnostic status output ? uvlo and ovlo functions ? programmable input deglitch filter ? asynchronous stop command ? programmable deadtime, with violation error ? spi interface for parameters programming ? temperature warning and shutdown protection ? self-diagnostic routines for protection features ? compact and simplified layout ? full effective fault protection applications ? 600/1200 v inverters ? industrial drives ? ups equipment ? dc/dc converters ? solar inverters description the STGAP1S gapdrive ? is a galvanically isolated single gate driver for n-channel mosfets and igbts with advanced protection, configuration and diagnostic features. the architecture of the STGAP1S isolates the channel from the control and the low voltage interface circuitry through true galvanic isolation. the gate driver is characterized by 5 a capability, making the device also suitable for high power inverter applications such as motor drivers in industrial drives. the output driver section provides a rail-to-rail out put with the possibility to use a negative gate driver supply. the input to output propagation delay results contained within 100 ns, providing high pwm control accuracy. protection functions such as the miller clamp, desaturation detection, dedicated sense pin for overcurrent detection, output 2-level turn-off, v ce overvoltage protection, uvlo and ovlo are included to easily desi gn high reliability systems. open drain diagnostic outputs are present and detailed device conditions can be monitored through the spi. each fu nction's parameter can be programmed via the spi, making the device very flexible and allowing it to fit in a wide range of applications. separate sink and source outputs provide high flexibility and bill of materi al reduction for external components. so24w www.st.com
contents STGAP1S 2/70 docid027190 rev 1 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 ac operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 dc operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 logic supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 low voltage section voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 high voltage section voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.3 power-up, power-down and ?safe state? . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 deadtime and interlocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.4 power supply uvlo and ovlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.5 thermal warning and shutdown protection . . . . . . . . . . . . . . . . . . . . . . . 31 7.6 desaturation protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.7 v ce active clamping protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.8 sense overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.9 miller clamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid027190 rev 1 3/70 STGAP1S contents 70 7.10 2-level turn-off function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.10.1 always . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.10.2 fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7.10.3 never . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.11 failure management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.12 asynchronous stop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.13 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.14 security check functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.14.1 gon to gate path check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.14.2 goff to gate path check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.14.3 sense comparator check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.14.4 sense resistor check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.14.5 desat comparator check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.15 register corruption protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 crc protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 programming manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1 spi commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1.1 startconfig and stopconfig commands . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.1.2 writereg command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1.3 readreg command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.1.4 resetreg, resetstatus and globalreset commands . . . . . . . . . . . . . . 50 9.1.5 sleep command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.1.6 nop command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2 registers and flags description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.2.1 cfg1 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.2.2 cfg2 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.2.3 cfg3 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2.4 cfg4 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.2.5 cfg5 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.6 status1 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.2.7 status2 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
contents STGAP1S 4/70 docid027190 rev 1 9.2.8 status3 register (low voltage side) . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9.2.9 test1 register (isolated side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 9.2.10 diag1 and diag2 registers (low voltage side) . . . . . . . . . . . . . . . . . . . 63 10 typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
docid027190 rev 1 5/70 STGAP1S list of tables 70 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 4. recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. ac operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) . . . . . . . . . . . . . . . . . . . . . . . . 13 table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) . . . . . . . . . . . . . . . . . . . . . . . . 14 table 7. isolation and safety-related specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 8. iec 60747-5-2 isolation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 table 9. isolation voltage as per ul 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. inputs true table (device not in ?safe state?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 11. crc byte examples (from host to device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 12. crc byte examples (from device to host) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 13. spi commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 14. startconfig command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 15. stopconfig command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 16. writereg command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 17. readreg command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 18. resetreg command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 19. resetstatus command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table 20. globalreset command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 0 table 21. sleep command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 22. nop command synopsis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 23. registers map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 24. cfg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 25. crc enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 26. vdd supply voltage uvlo enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 table 27. sd pin fault management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 28. in-/diag2 pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 29. deadtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 30. input deglitch time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 31. cfg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. sense threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 33. desat current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 34. desat threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 35. cfg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 36. 2ltoth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 37. 2-level turn-off time value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 38. cfg4 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 39. vh and vl supply voltages ovlo enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 40. uvlo protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 41. vl negative supply voltage uvlo threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 42. vh positive supply voltage uvlo threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 43. cfg5 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 44. 2lto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 45. sense comparator enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 46. desat comparator enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
list of tables STGAP1S 6/70 docid027190 rev 1 table 47. miller clamp feature enabling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 48. status1 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 49. status1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 50. status2 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 51. status2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 52. status3 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 53. status3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 54. test1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 55. check mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 56. diag1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 57. diag2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 58. relation between diag1/2 bits and failure conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 59. so24w package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 60. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 61. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
docid027190 rev 1 7/70 STGAP1S list of figures 70 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. low voltage section 3.3 v voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. high voltage section 3.3 v voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. hw cross conduction prev ention in half-bridge configuration with two single gate drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 6. transitions causing the dt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 7. synchronous control signal edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 8. control edges signal overlapped, example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 9. control edges signal overlapped, example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 10. control edges signal not overlapped and outside dt (direct control) . . . . . . . . . . . . . . . . . 29 figure 11. desat protection timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 12. example of v ce active clamping protection connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 13. vceclamp timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 14. example of short turn-on pulses when 2lto o ccurs at each cycle . . . . . . . . . . . . . . . . . . 35 figure 15. example of short turn-off pulse when 2lto occu rs at each cycle . . . . . . . . . . . . . . . . . . . 35 figure 16. example of operation with 2lto in ?fault? mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17. gate paths check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 18. sense comparator and resistor check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 19. desat comparator check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. spi timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 21. spi daisy chain connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 22. spi daisy chain connection example when bootstrap technique is used for high-side drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 figure 23. block diagram of the crc genera tor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 24. typical application diagram in half-bridge configur ation . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 25. so24w package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26. so24w suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
block diagram STGAP1S 8/70 docid027190 rev 1 1 block diagram figure 1. block diagram i s o l a t i o n level shifter floating section control logic floating ground uvlo vh uvlo vl desat vh vregiso gon goff vl clamp gndiso sense asc vceclamp spi sd vdd vdd vreg gnd sdo 3v3 voltage reg v desatth i desat + v 2ltoth v clampth + + ck sdi control logic in+ diag1 in-/diag2 v senseth + cs
docid027190 rev 1 9/70 STGAP1S pin connection 70 2 pin connection figure 2. pin connection (top view) table 1. pin description pin no. pin name type function 7 vdd power supply internal 3.3 v regulator input supply pin 6 vreg power supply internal 3.3 v regulator output and supply pin 11 sd logic input shutdown input (active low) 9 in+ logic input gate command input 8 in-/diag2 logic input/open drain output gate command input /open drain diagnostic output 10 diag1 open drain output open drain diagnostic output 1, 12 gnd ground low voltage section ground 4cs logic input spi chip select (active low) 5 ck logic input spi clock 3 sdi logic input spi serial data input 2 sdo logic output spi serial data output 19 vceclamp analog input v ce active clamping protection 18 desat analog input desaturation protection 15 vregiso power supply internal regul ator output pin for decoupling 17 vh power supply positive voltage supply 20 gon analog output gate source output 21 goff analog output gate sink output 22 clamp analog output miller clamp sdi sdo gnd 1 3 2 clamp vl asc 24 23 22 21 ck desat vceclamp gon 20 19 18 17 5 7 6 8 vh in+ 16 9 15 10 14 11 13 12 goff 4 vdd gnd vreg vl vregiso sense gndiso diag1 in-/diag2 cs sd
pin connection STGAP1S 10/70 docid027190 rev 1 14, 23 vl power supply negative supply voltage or ground 13 gndiso ground high voltage section (isolated) ground 16 sense analog input sense input for overcurrent protection 24 asc analog input asynchronous stop command table 1. pin description (continued) pin no. pin name type function
docid027190 rev 1 11/70 STGAP1S electrical data 70 3 electrical data 3.1 absolute maximum ratings table 2. absolute maximum ratings symbol parameter test condition min. max. unit dv iso /dt common mode transient immunity v cm = 1500 v 50 v/ns vdd integrated 3.3 v voltage regulator input voltage vs. gnd -0.30 6.50 v vreg integrated 3.3 v voltage regulator output voltage vs. gnd -0.30 3.60 v vreg_iso isolated logic supply voltage vs. gndiso -0.30 3.60 v v logic logic pins voltage vs. gnd -0.30 vdd + 0.30 v vhl differential supply voltage (vh vs. vl) -0.30 40 v vh positive supply voltage (vh vs. gndiso) -0.30 40 v vl negative supply voltage (vl vs. gndiso) -15 0.30 v v out voltage on gate driver outputs (gon, goff, clamp vs. vl) vl - 0.30 vh + 0.30 v v desat voltage on desat pin vs. gndiso -0.30 vh + 0.30 v v sense voltage on sense pin vs. gndiso -2 (vh + 0.30, 20) min v v ceclamp voltage on vceclamp pin vs. vl vl - 0.30 vh + 0.30 v v asc voltage on asc pin vs. gndiso -0.30 vh + 0.30 v i diagx open drain dc output current v diagx < 0.8 v 20 ma v diagx open drain output voltage -0.30 6.50 v t j junction temperature -40 150 c t s storage temperature -50 150 c t a ambient temperature -40 125 c p din power dissipation input chip f sw = 1 mhz 65 mw p dout power dissipation output chip (t j,max - t a )/r th(ja) - p din w dh/dt magnetic field immunity 100 a/(ms) esd human body model 2 kv
electrical data STGAP1S 12/70 docid027190 rev 1 3.2 thermal data 3.3 recommended operating conditions table 3. thermal data symbol parameter value unit r th(ja) thermal resistance junction to ambient (1) 65 c/w 1. the STGAP1S mounted on the evalSTGAP1S rev 2.0 board (two-layer fr4 pcb). table 4. recommended operating conditions symbol pin parameter test condition min. max. unit vh 17 positive supply voltage (vh vs. gndiso) 4.50 (1) 36 v vl 14, 23 negative supply voltage (vl vs. gndiso) gndiso - 10 gndiso (2) v vhl differential supply voltage (vh vs. vl) 36 v vdd 7 integrated 3.3 v voltage regulator input voltage vs. gnd 4.50 5.50 v vreg 6 internal logic supply voltage vs. gnd (3) 33.60v v logic 2, 3, 4, 5, 8, 9, 11 logic pins voltage vs. gnd (vdd, 5) min v asc 24 asc pin voltage gndiso (vh, 15) min v v desatth 18 desaturation protection threshold desat enabled vh - 1.50 v f sw maximum switching frequency 1 mhz 1. when uvlo is enabled this value is vh on,max . 2. when uvlo is enabled this value is vl on,min . 3. when vdd is connected to the vreg pin (refer to section 6 on page 23 ).
docid027190 rev 1 13/70 STGAP1S electrical characteristics 70 4 electrical characteristics 4.1 ac operation table 5. ac operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) symbol pin parameter test condition min. typ. max. unit t deglitch 8, 9, 11 input deglitch time infilter = '11' 50 70 90 ns infilter = '01' 140 210 280 ns infilter = '10' 490 560 630 ns t inmin minimum propagated input pulse infilter = '00' and (2lto_en = '0' or 2ltotime = 0x0) 20 ns t don 8, 9, 11, 20 input to output propagation delay on deglitch filter and 2lto disabled 90 100 130 ns t doff 8, 9, 11, 21 input to output propagation delay off deglitch filter and 2lto disabled 90 100 130 ns t r 20 gon rise time vl = 0 v; c l = 2 nf, 10% 90% 25 ns t f 21 goff rise time vl = 0v c l = 2 nf, 90% 10% 25 ns pwd 8, 9, 11, 20, 21 pulse width distortion |t don - t doff | t in > 100 ns deglitch filter and 2lto disabled 410ns dt 8, 9, 20, 21 deadtime dtset = '01' 205 250 295 ns dtset = '10' 650 800 945 dtset = '11' 985 1200 1415 t release 11 minimum flag release time sd = '0' 105 s
electrical characteristics STGAP1S 14/70 docid027190 rev 1 4.2 dc operation table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) symbol pin parameter test condition min. typ. max. unit logic inputs/output v ol 2 sdo logic ?0? output voltage i = 4 ma 0.15 v v oh sdo logic ?1? output voltage i = 4 ma 4.85 v i inh 8, 9 inx logic ?1? input bias current v in = 5 v (pin 8 used as in-) 55 85 145 a i inl inx logic ?0? input bias current v in = 0 v (pin 8 used as in-) 0.10 a i sdh 11 sd logic ?1? input bias current v sd = 5 v 55 85 145 a i sdl sd logic ?0? input bias current v sd = 0 v 0.10 a r in_pd 8, 9, 11 input pull-down resistors v in = 5 v (pin 8 used as in-) 35 60 85 k ? r in_pu 4 cs input pull-up resistor cs = gnd 35 55 80 k ? v il 3, 4, 5, 8, 9, 11 low logic level voltage 0.29 vdd 0.33 vdd 0.37 vdd v v ih high logic level voltage 0.62 vdd 0.66 vdd 0.79 vdd v driver buffer section i gon 20 source short-circuit current v in < v ih , tpulse < 5 ? s, dc = 1 % t j = 25 c t j = -40 +125 c 2.50 5 7 a i goff 21 sink short-circuit current v in < v ih , tpulse < 5 ? s, dc = 1 % t j = 25 c t j = -40 +125 c 2.50 5 6 a v goffl 21 goff output low level voltage i goff = 0.1 a i goff = 1 a vl + 0.03 vl + 0.50 vl + 0.09 vl + 1 vl + 0.15 vl + 1.80 v v gonh 20 gon output high level voltage i gon = 0.1 a i gon = 1 a vh - 0.18 vh - 2.10 vh - 0.10 vh - 1.30 vh - 0.05 vh - 0.50 v safeclp 20, 21, 22 goff active clamp i goff = 0.2 a; vh floating; gon = goff = clamp 3v
docid027190 rev 1 15/70 STGAP1S electrical characteristics 70 supply voltage i reg 6 vreg short-circuit current (see section 7.3 on page 30 ) 0.1 v < vreg < 3.0 v 60 120 ma vreg < 0.1 v 15 35 vdd on 7 vdd uvlo turn-on threshold 3.95 4.10 4.30 v vdd off vdd uvlo turn-off threshold 3.65 3.80 4 v vdd hys vdd uvlo hysteresis 0.15 v ovvdd on vdd ovlo turn-on threshold 5.30 5.50 5.90 v ovvdd off vdd ovlo turn-off threshold 5.40 5.70 6.10 v ov vddhys vdd ovlo hysteresis 100 200 300 mv i qdd 7 vdd quiescent supply current vdd = 5 v; sd = 5 v; inx = gnd; f = 0 hz 5.20 6.50 7.50 ma vdd = 5 v; sd = 5 v; f sw = f sw,max 7.50 8.50 9.50 ma vh on 17 vh uvlo turn-on threshold vhonth = '01' 9.40 10 10.50 v vhonth = '10' 11.30 12 12.60 vhonth = '11' 13.15 14 14.70 vh off vh uvlo turn-off threshold vhonth = '01' 8.50 9 9.45 v vhonth = '10' 10.35 11 11.55 vhonth = '11' 12.25 13 13.65 vh hyst vh uvlo hysteresis 0.70 1 1.30 v vl on 14, 23 vl uvlo turn-on threshold vlonth = '01' -3.15 -3 -2.80 v vlonth = '10' -5.25 -5 -5.70 vlonth = '11' -7.35 -7 -6.55 vl off vl uvlo turn-off threshold vlonth = '01' -2.15 -2 -1.90 v vlonth = '10' -4.25 -4 -3.80 vlonth = '11' -6.35 -6 -5.70 vl hys vl uvlo hysteresis 0.70 1 1.20 v table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) (continued) symbol pin parameter test condition min. typ. max. unit
electrical characteristics STGAP1S 16/70 docid027190 rev 1 ov vhoff 17 vh ovlo turn-off threshold ovlo_en = '1' 17.80 19 20 v ov vhon vh ovlo turn-on threshold ovlo_en = '1' 16.90 18 18.90 v ov vhhys vh ovlo hysteresis ovlo_en = '1' 0.60 1 1.30 v ov vloff 14, 23 vl ovlo turn-off threshold ovlo_en = '1' -10.50 -10 -9.40 v ov vlon vl ovlo turn-on threshold ovlo_en = '1' -9.45 -9 -8.55 v ov vlhyst vl ovlo hysteresis ovlo_en = '1' 0.70 1 1.30 v i qh 17 vh quiescent supply current sd = 5 v; in+ = 5 v; in- = gnd 5 6.70 7.50 ma sd = 5 v; f sw = f sw,max ; no load 10 14 19 ma i ql 14, 23 vl quiescent supply current vl = -5 v; sd = 5 v; in+ = in- = gnd 300 420 550 ? a vl = -5 v; sd = 5 v; f sw = f sw,max; no load tbd ? a table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) (continued) symbol pin parameter test condition min. typ. max. unit
docid027190 rev 1 17/70 STGAP1S electrical characteristics 70 desaturation protection v desatth 18 desaturation threshold desatth = '000'; 2.60 3 3.10 v desatth = '001' 3.60 4 4.20 desatth = '010' 4.60 5 5.30 desatth = '011' 5.50 6 6.30 desatth = '100' 6.50 7 7.40 desatth = '101' 7.40 8 8.40 desatth = '110' 8.30 9 9.40 desatth = '111' 9.30 10 10.50 t desfilter desat pin deglitch filter desatth = '100' (1) 10 20 30 ns i desat desat blanking charge current desatcur = '00' 220 250 265 a desatcur = '01' 440 500 525 desatcur = '10' 660 750 800 desatcur = '11' 885 1000 1050 i desoff desat blanking discharge current v desat = 8 v 50 70 90 ma t blk desat protection fixed blanking time 160 250 340 ns t desat desat protection intervention time v desat = v desath to goff 90% c load = 10 nf 80 150 220 ns sense overcurrent function v senseth 16 sense protection threshold senseth = '000' 88 100 112 mv senseth = '001' 110 125 140 senseth = '010' 135 150 165 senseth = '011' 158 175 192 senseth = '100' 185 200 215 senseth = '101' 235 250 268 senseth = '110' 285 300 315 senseth = '111' 380 400 420 t sense sense protection intervention time senseth = '111' 0 ? 1 v step on v sense to goff 90%; c load = 10 nf 95 120 ns table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) (continued) symbol pin parameter test condition min. typ. max. unit
electrical characteristics STGAP1S 18/70 docid027190 rev 1 2-level turn-off function v 2ltoth 21 2lto threshold 2ltoth = '0000' 6.65 7.00 7.35 v 2ltoth = '0001' 7.12 7.50 7.88 2ltoth = '0010' 7.60 8.00 8.40 2ltoth = '0011' 8.07 8.50 8.93 2ltoth = '0100' 8.55 9.00 9.45 2ltoth = '0101' 9.02 9.50 9.98 2ltoth = '0110' 9.50 10.00 10.50 2ltoth = '0111' 9.97 10.50 11.03 2ltoth = '1000' 10.45 11.00 11.55 2ltoth = '1001' 10.92 11.50 12.08 2ltoth = '1010' 11.40 12.00 12.60 2ltoth = '1011' 11.87 12.50 13.13 2ltoth = '1100' 12.35 13.00 13.65 2ltoth = '1101' 12.82 13.50 14.18 2ltoth = '1110' 13.30 14.00 14.70 2ltoth = '1111' 13.77 14.50 15.23 t 2ltotime 2lto time 2ltotime = '0001' 0.64 0.75 0.89 s 2ltotime = '0010' 0.89 1.00 1.15 2ltotime = '0011' 1.36 1.50 1.65 2ltotime = '0100' 1.83 2.00 2.18 2ltotime = '0101' 2.30 2.50 2.70 2ltotime = '0110' 2.77 3.00 3.23 2ltotime = '0111' 3.25 3.50 3.75 2ltotime = '1000' 3.47 3.75 4.03 2ltotime = '1001' 3.71 4.00 4.29 2ltotime = '1010' 3.94 4.25 4.56 2ltotime = '1011' 4.18 4.50 4.82 2ltotime = '1100' 4.42 4.75 5.08 2ltotime = '1101' 4.66 5.00 5.34 2ltotime = '1110' 4.90 5.25 5.63 2ltotime = '1111' 5.12 5.50 5.95 table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) (continued) symbol pin parameter test condition min. typ. max. unit
docid027190 rev 1 19/70 STGAP1S electrical characteristics 70 diagnostic outputs t diag1,2 8, 10 fault event to diagx low delay fault event to diagx 90% 5tbds i diag1 diag1 low level sink current v diag1 = 0.4 v 10 18 30 ma i diag2 diag2 low level sink current v diag2 = 0.4 v 10 18 30 ma r diag1,2 diagx pull-down resistor 300 550 800 k ? clamp miller function v clampth 22 clamp voltage threshold clamp vs. gndiso 1.70 2 2.30 v i clamp clamp short-circuit current v in < v ih , tpulse < 5 ? s, dc = 1 % t j = 25 c t j = -40 +125 c 2.50 5 6 a v clamp_l clamp low level output voltage i clamp = 1 a vl + 0.50 vl + 1 vl + 1.80 v v ce active clamping protection v vceclth 19 v ce clamping threshold vl + 1.20 vl + 1.60 vl + 2 v v vceclhyst v ce clamping threshold hysteresis 0.30 0.50 0.60 v t vcecloff v ce clamping time- out 2 2.30 2.60 s t vcecl v ce clamping intervention time 20 ns asc function v ascl 24 low logic level voltage 0.80 1.10 1.40 v v asch high logic level voltage 1.80 2.20 2.40 v i asch asc logic ?1? input bias current v asc = 5 v 55 100 145 a i ascl asc logic ?0? input bias current v asc = 0 v 0.10 a r asc asc pull-down resistors v asc = 5 v 35 50 70 k ? t asc asc intervention time v asc = 5 v 100 250 ns table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) (continued) symbol pin parameter test condition min. typ. max. unit
electrical characteristics STGAP1S 20/70 docid027190 rev 1 functionality checks t gchk 20, 21 gate path check time (gon/goff) (2) (2) 30 s v gchk 20 gate path check voltage (gon) 0.7 x vh 0.76 x vh 0.84 x vh v t rchk 16 sense resistor check time 15 s i goffchk 21 goff path check current -420 -350 -280 a i senserchk 16 sense resistor check current v sense < 1 v 8 10 12 a t sensechk sense comparator check time 15 s t desatchk 18 desat comparator check time 15 s overtemperature protection t wn warning temperature 125 c t sd shutdown temperature (1) 155 c t hys temperature hysteresis (1) 20 c standby i stby_vdd 7 vdd standby current vdd = 5 v 0.40 0.80 1 ma t sleep standby time sd = '0' 500 700 900 ns t awake logic wake-up time (1) sd = '1' 5 s spi t ckmax 5 maximum spi clock frequency 5mhz t rck t fck spi clock rise and fall time cl = 30 pf 25 ns t hck t lck spi clock high and low time 75 ns t setcs 4 cs setup time 350 ns t holcs cs hold time 10 ns t descs cs deselect time (3) local register read 800 ns remote register read 30 s t setsdi 3 sdi setup time 25 ns t holsdi sdi hold time 20 ns table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) (continued) symbol pin parameter test condition min. typ. max. unit
docid027190 rev 1 21/70 STGAP1S electrical characteristics 70 t ensdo 2 sdo enable time 38 ns t dissdo sdo disable time 47 ns t vsdo sdo valid time 57 ns t holsdo sdo hold time 37 ns 1. characterization data, not tested in production. 2. the actual waiting time depends on the gate charge size. 3. see table 23 on page 52 and section 9.1.3 on page 49 . table 6. dc operation electrical characteristics (t j = -40 to 125 c, vdd = 5 v; vh = 15 v, vl = gndiso) (continued) symbol pin parameter test condition min. typ. max. unit
isolation STGAP1S 22/70 docid027190 rev 1 5 isolation table 7. isolation and safety-related specifications parameter symbol value unit conditions clearance (minimum external air gap) clr tbd mm measured from input terminals to output terminals, shortest distance through air creepage (minimum external tracking) cpg 8 mm measured from input terminals to output terminals, shortest distance path along body comparative tracking index (tracking resistance) cti ? 400 din iec 112/vde 0303 part 1 isolation group ii material group (din vde 0110, 1/89, table 1) table 8. iec 60747-5-2 isolation characteristics parameter symbol test conditions characteristic unit installation classification (en 60664-1, table 1 - see (1) ) for rated mains voltage ? 150 v rms for rated mains voltage ? 300 v rms for rated mains voltage ? 600 v rms i - iv i - iii i - ii climatic classification tbd pollution degree (en 60664-1) 2 maximum working isolation voltage v iorm 1500 v peak input to output test voltage as per iec 60747-5-2 v pr method a, type test v pr = v iorm 1.6, t m = 10 s partial discharge < 5 pc 2400 v peak method b, 100 % production test v pr = v iorm 1.875, t m = 1 s partial discharge < 5 pc 2815 v peak transient overvoltage as per iec 60747-5-2 (highest allowable overvoltage) v iotm t ini = 60 s type test 4000 v peak maximum surge isolation voltage v iosm type test 4000 v peak isolation resistance r io v io = 500 v at t s >10 9 ? 1. for three-phase systems the values in t he table refer to the line-to-neutral voltage. table 9. isolation voltage as per ul 1577 description symbol characteristic unit isolation withstand voltage, 1 min. (type test) v iso 2500\3536 v rms \v peak isolation withstand test, 1 sec. (100% production) v isotest 3000\4245 v rms \v peak
docid027190 rev 1 23/70 STGAP1S logic supply management 70 6 logic supply management 6.1 low voltage sectio n voltage regulator the device integrates in the low voltage section a linear voltage regulator that can be used to obtain the 3.3 v logic core supply voltage from an external 5 v supply voltage. if an external 3.3 v supply voltage is available th e vdd and vreg have to be shorted as shown in figure 3 . the logic ios are referred to the vdd voltage (see table 6 on page 14 for details). figure 3. low voltage section 3.3 v voltage regulator undervoltage protection is available on th e vdd supply pin (disabled by default). when the vdd voltage goes below the vdd off threshold the device and its outputs goes in ?safe state? (see section 6.3 ) and the uvlod status flag is fo rced low. once the protection is triggered, the uvlod flag is latched and the device remains in ?safe state? until the uvlod flag is not released. see section 7.11 on page 36 for indication on how the failure flags can be released. this protection can be enabled writing the uvlo d_en bit of the cfg1 register (disabled by default). overvoltage protection is available on the vdd supply pin. when the vdd voltage goes over the ov vddoff threshold the device an d its outputs goes in ?safe state? and the ovlod status flag is forced low. the device remains in ?safe state? and the ovlod flag is latched, see section 7.11 for indication on how the failure flags can be released. vreg vdd +5v ldo reg 4.7 f 100 nf 100 nf 4.7 f vdd from +5 v power supply vreg vdd +3.3v ldo reg 4.7 f 100 nf vdd from +3.3 v power supply
logic supply management STGAP1S 24/70 docid027190 rev 1 6.2 high voltage section voltage regulator the device integrates in the high voltage section a linear voltage regulator that generates the 3.3 v logic core supply voltage from an ex ternal supply voltage connected to the vh pin. figure 4. high voltage section 3.3 v voltage regulator if the voltage at the vregiso pin goes below the minimum operating threshold which causes the logic reset, the reg_err bit in the status1 register is set high. 6.3 power-up, power-do wn and ?safe state? the following conditions define the device's ?safe state?: ? goff = on state ? gon = high impedance ? clamp = on state (if clamp < 'gndiso + v clampth ') ? desat = gndiso (internal switch on and current generator off) such conditions are guaranteed at power-up of the isolated side (also for vh < vh on and vl > vl on ) and during the whole device power-down phase (also for vh < vh off and vl > vl off ), whatever the value of the input pins. the device integrates a structure which clamps the driver output to a voltage smaller than safeclp when the vh voltage is not high en ough to actively turn the goff n-channel mosfet on. if the vh positive supply pin is floating the goff pin is clamped to a voltage smaller than safeclp. after power-up of the isolated side the regerrr status flag is latched and the device is forced in ?safe state?. see section 7.11 on page 36 for indication on how the failure flags can be released. after power-up of the low voltage side the regerrl and uvlod status flags are latched and the device is forced in ?safe state?. see section 7.11 for indication on how the failure flags can be released. the uvloh flag is also forced high at the powe r-up of the low voltage side, but its value is set to zero as soon as the isolated side power-up is completed. vregiso vh vh ldo reg 4.7 f 100 nf 100 nf
docid027190 rev 1 25/70 STGAP1S logic supply management 70 6.4 standby function the device can be put in sleep mode to reduce the power consumption on vdd via a spi command (refer to section 9.1.5 on page 50 ). the proper sequence is: 1. pull-down the sd pin: the driver section will be put in ?safe state? 2. send a sleep command 3. after a t sleep time the device can be consider ed actually in the sleep mode. to exit from the sleep mode it is necessa ry a transition low-to-high on the sd pin. after a t awake time the device can accept new commands and/or signals depending on the boundary conditions. after exiting sleep mode the regerrr is set to indicate that th e device needs to be reprogrammed. if during the switching between operation and lo w consumption modes the sd pin is raised, the device returns to the operation mode within a t awake time.
functional description STGAP1S 26/70 docid027190 rev 1 7 functional description 7.1 inputs and outputs the device is controlled through following logic inputs: ? sd: active low shutdown input ? in+: driver input ? cs: active low chip select (spi) ? sdi: serial data input (spi) ? ck: serial clock (spi) and following logic outputs: ? sdo: serial logic output (spi) ? diag1: diagnostic signal (open drain) and following io pin: ? in-/diag2: driver input or diagnostic open drain output. logic input thresholds and output ranges vary according to vdd voltage. in particular, the device is designed to work with vdd supply voltages of 5 v or 3.3 v. the operation of the driver ios can be prog rammed through diag_en bits as described in table 10 . a deglitch filter is applied to device inputs (sd, in+, in-). each input pulse, positive and negative, shorter than the programmed t deglitch value is neglected by internal logic. deglitch time can be pr ogrammed as listed in table 30 on page 53 . when the deglitch filter is disabled (infilter = ' 00') and the 2-level turn-off function is disabled (2ltotime = 0x0) or enabled only after a fault event (2lto_en = '0'), a minimum input pulse t inmin is required to change the device output status. the minimum input pulse timing filters out both positive and negative pul ses at in+, in- and sd pins. table 10. inputs true table (device not in ?safe state?) bit in cfg1 register input pins output pins diag_en sd in+ in- gon goff x0xxoffon 0100offon 0101offon 0 1 1 0 on off 0111offon 110x (1) 1. the in-/diag2 pin is used as the open drain output for diagnostic signaling (refer to section 7.11 on page 36 ). off on 111x (1) on off
docid027190 rev 1 27/70 STGAP1S functional description 70 7.2 deadtime and interlocking when single gate drivers are used in half-bri dge configuration, they usually do not allow preventing cross conduction in case of wrong input signals coming from the controller device. this limitation is due to the fact that each driver does not have the possibility to know the status of the input signal of the other companion driver in the same leg. thanks to the availability of two input pins with opposi te polarity the STGAP1S allows implementing an hardware interlocking that prevents cross conduction even in case of wrong input signals generated by the control unit. this functi onality can be achieved by implementing the connection shown in figure 5 and by configuring the in-/diag2 pin as input (which is its default configuration). figure 5. hw cross conduction prevention in half-bridge configuration with two single gate drivers when such configuration is used, it is also possible to enable the STGAP1S programmable deadtime feature, which guarantees that at least a dt time passes between the turn-off of one driver's output and the turn-on of the other driver. the deadtime value dt can be programmed through the spi interface as shown in table 29 on page 53 . if the deadtime feature is enabled, a counter is started when the input status changes from < in- = '1' and in+ = '0' > to a different combination, which means that the other driver in the same leg is at the beginning of a turn-off (refer to figure 6 ). once the counter is started it keeps counting regardless of any input variation until a dt time has passed, and during this time the driver prevents the turn-on of its output even if the controller tries to force th e turn-on (inputs set to < in- = '0' and in+ = '1' >). once the programmed dt counter is expired, th e driver immediately turns the output on as soon as a turn-on command is present at the input pins, and no extra delay is added c hin lin in+ in- gapdrive hs in+ in- gapdrive ls
functional description STGAP1S 28/70 docid027190 rev 1 figure 6. transitions causing the dt generation transitions causing the dt generation in- = 0 in+ = 0 in- = 0 in+ = 1 in- = 1 in+ = 0 in- = 1 in+ = 1 this driver on paired driver on all off all off
docid027190 rev 1 29/70 STGAP1S functional description 70 some examples of the device behavior when the deadtime feature is enabled are shown from figure 7 to figure 10 . figure 7. synchronous control signal edges figure 8. control edges signal overlapped, example 1 figure 9. control edges signal overlapped, example 2 figure 10. control edges signal not overlapped and outside dt (direct control) when the deadtime function is enabled the st gap1s reports a ?deadtime violation? fault in case the control unit tr ies to turn on any of the drivers in one leg during the counting of the programmed dt time. if such event occurs the dt_err flag is set high and latched. dt in- in+ gon-goff dt control signals edges; synchronous dead time dt in- in+ gate dt control signals edges overlapped; dead time dt dt in- in+ gon-goff dead time dt control signals edges not overlapped, but inside the dead time: dt in- in+ gon-goff dt control signals edges not overlapped, outside the dead time: direct driving
functional description STGAP1S 30/70 docid027190 rev 1 7.3 hardware reset the device can be reset by forcing the vreg pin to ground through an external switch. the internal regulator is designed to stand this condition. the maximum current required to force the vreg pin to ground is indicated by the parameter i reg . 7.4 power supply uvlo and ovlo undervoltage protection is available on both vh and vl supply pins. the turn-on threshold can be programmed through the spi writing the cfg4 register. a fixed 1 v hysteresis will set the respective turn-off threshold. both uvlo protections can be independently disabled by setting the proper value in the cfg4 register. when vh voltage goes below the vh off threshold the output buffer goes in ?safe state? and the uvloh status flag is forced high. if the uv lolatch bit in the cfg4 register is set low (default), the uvloh status flag is released when vh voltage reaches the vh on threshold and the device returns to normal operation. otherwise the uvloh flag is latched and the device remains in ?safe state? until the vh voltage reaches the vh on threshold and the flag is released. see section 7.11 on page 36 for indication on how the failure flags can be released. when vl voltage goes over the vl off threshold the output buffer goes in ?safe state? and the uvlol status flag is forced high. if the uvlo latch bit in the cfg4 register is set low (default), the uvlol status flag is released when vl voltage goes below the vlon threshold and the device returns to normal operation. otherwise the uvlol flag is latched and the de vice remains in ?safe state? until the vl voltage goes below the vl on threshold and the flag is released. see section 7.11 for indication on how the failure flags can be released. overvoltage protection is available on both vh and vl supply pins. both ovlo protections can be disabled by setting the proper value in the cfg4 register. when the vh voltage goes over the ov vhoff threshold the output buffer goes in ?safe state? and the ovloh status flag is forced high. the ovloh flag is latched and the device remains in ?safe state? until vh voltage goes below the overvoltage threshold and the flag is released. see section 7.11 for indication on how the fa ilure flags can be released. when vl voltage goes over the ov vloff threshold the output buffer goes in ?safe state? and the ovlol status flag is forced high. the ovlo l flag is latched and the device remains in ?safe state? until vh voltage goes below the ov ervoltage threshold and the flag is released. see section 7.11 for indication on how the failure flags can be released.
docid027190 rev 1 31/70 STGAP1S functional description 70 7.5 thermal warning and shutdown protection the device provides a thermal warning and a thermal shutdown protection. when junction temperature reaches the t wn temperature threshold the twn flag in the status1 register is forced high. the twn fl ag is released as soon as the junction temperature is lower than t wn - t hys . when junction temperature reaches the t sd temperature threshold, the device is forced in ?safe state? and the tsd flag in the status1 re gister is forced high. the device operation is restored and the tsd flag is released as soon as the junction temperature is lower than t sd - t hys . 7.6 desaturation protection this feature allows implementing an overlo ad protection for the igbt. the desat pin monitors the v ce voltage of the igbt while it is on, and if the protection threshold is reached, the igbt is turned off. when the igbt is off (goff output is activate d) the desat pin is ke pt low internally and the external blanking capacitor connected to the desat pin is discharged (the internal current generator is fully switched off and th e switch between desat and gndiso pins is turned on). when the gon output is activated the switch between desat and gndiso pins is turned off and an internal programmable current generator (i desat ) starts charging the external blanking capacitor after a fixed blanking time t blk . if a desaturation event occurs the v ce voltage increases and the voltage at the desat pin reaches the desaturation threshold v desatth : the desat comparator output is set, the device is forced in ?safe state? and th e desat flag is forced high and latched. the desat comparator is not active when the external igbt is off or after desaturation detection (see figure 11 ). both the v desatth threshold and the i desat blanking current are programmable through the spi.
functional description STGAP1S 32/70 docid027190 rev 1 figure 11. desat protection timing diagram a deglitch filter is applied to the desat pin. each pulse exceeding the v desatth for a time shorter than t desfilter value shall not trigger the protection. 7.7 v ce active clamping protection this protection is used to actively clamp t he drain/collector overvoltage spikes during the mosfet/igbt turn-off. this feat ure allows using low turn-off resistor values leading lower turn-off losses, thus increasing efficiency, wh ile limiting the maximum turn-off spike on the collector (or drain) within safe limits. the direct feedback of the collector voltage to the device can for example be made via an element with avalanche characteristics such as a tvs. if the vce voltage exceeds the breakdown voltage of the tvs, the v vceclth threshold voltage on the vceclamp is reached and the ic actively slows down the powe r switch turn-off to keep a safe condition. the active limiting of the driver's turn-off current strongly reduces the current flowing through the tvs, thus preventing it from operating in overstressing conditions. desat vh level diagx vl level blanking time comparator disabled comparator disabled comparator enabled t blk t desat in+ v desatth gon-goff t diagx
docid027190 rev 1 33/70 STGAP1S functional description 70 figure 12. example of v ce active clamping protection connection when the vceclamp is activated during the turn -off phase a watchdog timer starts inside the driver. this timer allows the vceclamp pi n to act on the driver's output status for a t vcecloff time maximum. after that time has expir ed, the driver continues the normal turn- off ignoring the vceclamp pin status. this assures that the protection is only acting to clamp inductive v ce spikes during the turn-off. the timer is reset and the vceclamp protection is enabled again at the beginning of the following turn-off sequence. figure 13. vceclamp timing diagram the vceclamp pin is masked and has no effect on the driver's outputs status when the external mosfet /igbt is on. floating section control logic vceclamp vh gon goff vl clamp gndiso clampth + vl vl vl level shifter t vcecloff gon\goff vceclamp vcecounter counting ready stopped ready stopped
functional description STGAP1S 34/70 docid027190 rev 1 a deglitch filter is applied to the vc eclamp pin. each pulse exceeding the v vceclth for a time shorter than t vceclfilter value shall not trigger the protection. the v ce active clamping protection can be disabled connecting the vceclamp pin to vl. 7.8 sense overcurrent protection this function is suitable in ap plications in which it is poss ible to measure the load current through the use of a shunt resistor, or in app lications that use igbts with the current sense pin available. the load current (or a fraction of it in case sensefets are used) is converted to voltage by an external shunt resistor a nd is fed to the sense pin (comparator input). when an overcurrent event occurs the sense voltage reaches the v senseth threshold, the device is forced in ?safe state? and the sense status flag is forced high and latched. the v senseth threshold is programmable through the spi (refer to section 9.2.2 on page 54 ). 7.9 miller clamp function the miller clamp function allows the control of the miller cu rrent during the power stage switching in half-bridge config urations. when the external power transistor is in the off state, the driver operates to avoid the induced turn-on phenomenon that may occur when the other switch in the same leg is being turned on, due to the c gc capacitance. during the turn-off period the gate of the external switch is monitored through the clamp pin. the clamp switch is activated when gate voltage goes below the voltage threshold v clampth , thus creating a low impedance path between the switch gate and the vl pin. this function can be disabled setting low the clamp_en bit in the cfg5 register (high by default). 7.10 2-level turn-off function if an overcurrent event happens, a large voltage overshoot exceeding v ce absolute ratings may occur across the power switch during the turn-off, due to the parasitic stray inductances. the 2-level turn-off function (2lto) allows the reduction of the stressing overvoltage experienced by the power component in overcurr ent condition by switch ing off the external power in two phases. in the first phase the goff voltage is actively forced to a programmable value v 2ltoth ; after a programmable delay t 2ltotime the goff is forced to vl to complete the gate turn-off. this allows to slow down the critical part of the turn-off transient, that may induce the overvoltage spikes. the voltage level v 2ltoth and duration t 2ltotime of the intermedia te off-level are programmable through the spi. it is possible to program when this feature takes place, refer to the following paragraphs.
docid027190 rev 1 35/70 STGAP1S functional description 70 7.10.1 always the 2lto is performed at each turn-off transition (2lto_en = '1'). when 2lto is used at each transition the mini mum on or off pulse width is determined by 2lto time. some sample waveforms are given in figure 14 and figure 15 , where in and represents the condition: < in+ = 'h' and in- = 'l' >. if a turn-on pulse is shorter than t 2ltotime it shall be ignored; turn-on pulses longer than t 2ltotime will determine a delay in the turn-on equal to t 2ltotime (see figure 14 ). figure 14. example of short turn-on pulses when 2lto occurs at each cycle when a turn-off pulse is detected the turn-off procedure starts immediately by forcing the v 2ltoth voltage on the goff pin. if the duration of the turn-off pulse is shorter than t 2ltotime the turn-off sequence is aborted by setting goff in high impedance and turning gon on again (see figure 15 ). figure 15. example of short turn-off pulse when 2lto occurs at each cycle when the 2lto is used at each cycle, any ev ent that forces the devi ce to enter in ?safe state? generates a driver switch off performing a 2lto sequence. 7.10.2 fault the 2lto is performed only after a desaturation or overcurrent event (2lto_en = '0'). in such cases the device enters in ?safe stat e? until the failure flag is released. see section 7.11 for indication on how the fa ilure flags can be released. t 2ltotime on time t 2ltotime t 2ltotime t 2ltotime t 2ltotime in and gon-goff t don on time on time t 2ltotime t don on time t doff t doff on-time < t 2ltotime on-time < t 2ltotime on-time > t 2ltotime on-time > t 2ltotime t 2ltotime t doff in and gon-goff t 2ltotime t doff t 2ltotime t doff t don off-time > t 2ltotime off-time < t 2ltotime off-time > t 2ltotime
functional description STGAP1S 36/70 docid027190 rev 1 this configuration overrides some drawbacks of using the 2lto at each turn-off, such as the minimum pulse width equal to t 2ltotime and the turn-on delay needed to avoid duty cycle distortion. with this configuration the tu rn-off is only slowed down in case of desaturation or overcurrent events. figure 16. example of operation with 2lto in ?fault? mode 7.10.3 never the 2lto function is disabled (2ltotime = 0x0). in this case a standard turn-off sequence is used (directly lowering the gate voltage from vh to vl) also in case of desaturation or sense overcurrent events. 7.11 failure management the device provides advanced diagnostic th rough open drain outputs (diag1/diag2) and internal status registers. the diag2 output shares the same pin of the in- input (see figure 1 on page 8 ); the diagnostic signal through the pin is enabled through the diag_en pin as described in section 7.1 on page 26 . status registers (status1, status2 and status3) provide failures and status information as listed in respective paragraphs. diag1 and diag2 pins can be programmed th rough the dedicated registers (diag1 and diag2) to signal one or more failure conditions . the output value is the result of the nor of the selected status bits: if one of the sele cted bits is high, the output is forced low. some of the failure conditions reported by the status registers are latched, i.e.: the flag is kept high even if the triggering condition is expired. in this case the failure flag can be released in following ways: ? using the resetstatus command (all flags are released) ? using the resetreg command on the respective status register (all flags of the register are released) ? forcing low the sd pin for at least t release when the sd_flag configuration bit is set high. all the flags are released at the sd rising edge. ? using hw reset (see section 7.3 on page 30 ). in this case the device behaves as after power-up sequence. t don t 2ltotime t doff t desat in and gon-goff v desatth desat t doff t don
docid027190 rev 1 37/70 STGAP1S functional description 70 in any case, if the failure co ndition is still present, the re spective flag is not released. selected failures force the device in ?safe stat e?; the device remains in this state until the relative status flags are released. refer to table 49 on page 60 , table 51 on page 61 and table 53 on page 62 for details. the possibility to clear status registers by se tting the sd low allows operating the device also without using the spi interfac e. in order to avoid an unintended clear of fault conditions it is recommended to disable this functionality by setting the sd_flag = '0'. 7.12 asynchronous stop command the asc pin allows to turn-on the gon output acti ng directly on the isolated driver logic and regardless of the status of the input pins in+, in- and sd. this pin is active high. the status of this pin is mirrored in th e asc bit present in the status2 register. the power supply of the isolated section must be present (vh > vh on ). in case uvlo on vh is not enabled, asc function works for vh values within the recommended operating values. this function works even if the vdd voltage is not available or is in uvlo condition. the priority of such command is lower than that of desat and sense pins, so the asc command is ignored in case of a desaturation or overcurrent fault. after such events the gate can be turned on again with a low-to-high transition of the asc pin, or by clearing the fault condition (see section 7.11 ). 7.13 watchdog the isolated side provides a watchdog function in order to identify when it is no more able to communicate with the lv side. in this case the dr iver is automatically forced in ?safe state? and the regerrr flag is forced high. when the lv side is in the standby mode, turned off or in hardware reset condition, the isolated side watchdog is still operative and an regerrr failure occurs. the low voltage side provides a watchdog function in order to identify when it is no more able to communicate with the isolated side. in this case the regerrl flag is forced high and the device is forced in ?safe state?. 7.14 security check functions the device allows verifying the gate and sense resistor connections and the functionality of sense and desat. this can be achieved through the followi ng security checks: ? gon to gate path ? goff to gate path ? sense comparator ? sense resistor ? desat comparator
functional description STGAP1S 38/70 docid027190 rev 1 the check modes are enabled through a dedicated configuration register test1 (refer to section 9.2.9 on page 62 ) and thus require entering in configuration mode. only one check mode at a time must be enabl ed. at the end of secu rity check procedure, the test1 register must be set to 0x00 before running the device in normal mode. it is recommended to clear the status register with the resetstatus command before and after each check. to prevent sd from clearing the status flags, set sd_flag = '0' as described in section 7.11 . 7.14.1 gon to gate path check the purpose of this security check is to verify the path integrity incl uding the driver's gon output, the gon (turn-on) gate resistor, the power switch gate and the clamp pin (see figure 17 ). to perform this test, the following procedure has to be followed: ? set sd = low ? send startconfig command ? set gonchk = '1' ? send stopconfig command ? wait t gchk ? read tsd flag ?tsd = '0' ok (v clamp > v gchk ) ?tsd = '1' fail (v clamp < v gchk ) please note that during all the time the check is enabled the gate will be forced high (gon turned on) regardless the sd pin level. the user test routine has to ta ke into account this behavior. in any case, when gonchk = '1', the prot ections sense and desat, if enabled, will continue to operate protecting the power switch regardless the sd pin. 7.14.2 goff to gate path check the purpose of this security check is to verify the path integrity incl uding the driver's goff output, the goff (turn-off) gate resistor, the power switch gate and the clamp pin (see figure 17 ). to perform this test, the following procedure has to be followed: ? set sd = low ? send startconfig command ? set goffchk = '1' ? send stopconfig command ? wait t gchk + t gate_goffchk ? read desat flag ? desat = '0' ok (v clamp < v clampth ) ? desat = '1' fail (v clamp > v clampth )
docid027190 rev 1 39/70 STGAP1S functional description 70 during the check a small current i goffchk will be sourced from the clamp pin while goff is on keeping the gate low through the turn-off gate resistor. to ensure the check result, some applicative conditions have to be verified: ? the bleeding resistor, sometimes present between the gate and source in the power switch, shall be lower than 8.2 k ? . ? during the test, the power switch gate shall have the time to be charged up to v clampth by i goffchk . in case no bleeding resistor is present, this time can be roughly computed as: t gate_goffchk c gate * (v clampth - vl) / i goffchk if a bleeding resistor is present or an additional push-pull circuit has been added, the time has to be computed with the adequate corrective factors. if the check fails due to the lack of the goff resistor, the power swit ch gate will gradually rise up to vh with no protections of sense nor desat. the user test routine shall consider this behavior. figure 17. gate paths check circuitry floating section control logic floating ground vh gon goff vl clamp gndiso v clampth + level shifter sd sdo ck cs sdi spi control logic i s o l a t i o n i goffchk vh test control
functional description STGAP1S 40/70 docid027190 rev 1 7.14.3 sense comparator check the purpose of this security check is to veri fy the functionality of the sense comparator. to enable this check, it is required to set snschk = '1' and sense_en = '1'. when this check is enabled the switch in series to the sense pin is open (see figure 18 ); a sense fault (status1 register) should be reported within t sensechk , otherwise the sense comparator operation is compromised. ? v sensecomp > v senseth comparator ok sense = '1' ? v sensecomp < v senseth comparator fail sense = '0' the sense fault generated by this test is latched and shall be cleared accordingly. figure 18. sense comparator and resistor check circuitry level shifter floating section control logic floating ground vh gon goff vl clamp gndiso sense v senseth + r test vh r sense test control sd sdo ck sdi i senserchk test control spi control logic i s o l a t i o n cs sensecomp
docid027190 rev 1 41/70 STGAP1S functional description 70 7.14.4 sense resistor check the purpose of this security check is to ve rify the connection betw een the device and the sense shunt resistor and to verify the optional sense resistor filter network is not open. to perform this test, the following procedure has to be followed: ? set sd = low ? send startconfig command ? set sense_en = '1' ? set goffchk = '1' ? send stopconfig command ? wait t rchk + t senserchk ? read sense flag ? sense = '0' ok (v sense < v senseth ) ? sense = '1' fail (v sense > v senseth ) during the check a small current i senserchk is sourced from the sense pin (see figure 18 ). if the sense resistor is not present or floating, sense pin voltage will rise and once v senseth is exceeded, a sense fault will be re ported in the status 1 register within t rchk . to ensure the check result, the following condition has to be verified: ? the sense flag read has to be delayed of t senserchk , which is the time the customer filtering network and/or the power switch gate takes to reach v senseth by the i senserchk current.
functional description STGAP1S 42/70 docid027190 rev 1 7.14.5 desat comparator check the purpose of this security check is to ve rify the functionality of the desaturation comparator. to perform this test, the following procedure has to be followed: ? set sd = low ? send startconfig command ? set desat_en = '1' ? set deschk = '1' ? send stopconfig command ? set sd = high ? wait 3 s ? apply at the inputs a gate turn on pulse longer than 500 ns ? read desat flag ? desat = '1' ok (v desatcomp > v desatth ) ? desat = '0' fail (v desatcomp < v desatth ) during this test gon is first turned on and then turned off as soon the test succeeds. in case the test should fail, the output remains on as long as the input signal remains high. at the end of the check the desat fault remains set (it is latched), and it has to be cleared. figure 19. desat comparator check circuitry floating section control logic floating ground desat vh gon goff vl clamp gndiso v desatth i desat + vh level shifter test control test control sd sdo ck sdi spi i s o l a t i o n 1k c blank cs in+ in- control logic
docid027190 rev 1 43/70 STGAP1S functional description 70 7.15 register corruption protection all the configuration registers are pr otected against content corruption. if the value of a local register is changed without a proper command is received ( writereg, resetreg or globalreset ), the regerrl flag is set lo w and the device is forced in ? safe state?. if the value of a remote register is changed without a proper command is received ( writereg, resetreg or globalreset ), the regerrr flag is set low and the device is forced in ?safe state?.
spi interface STGAP1S 44/70 docid027190 rev 1 8 spi interface the ic communicates with an external mcu thro ugh a 16-bit spi. this interface is used to set the device parameters and for advanced diagnostic. the spi i/o pins are: ? cs: chip select (active low) ? ck: serial clock ? sdi: serial data input (mosi) ? sdo: serial data output (miso). the interface is compliant with the spi standar d cpha = 1 and cpol = 0 (serial data is sampled on ck falling edge and it is updated on ck rising ed ge, at cs falling edge the ck signal must be low) as shown in figure 20 . figure 20. spi timings the spi interface can work up to 5 mbps and provides the daisy chain feature. in order to guarantee a safe operation and robustness to electrical noise, the number of rising edges within a cs negative pulse must be multiple of 16, otherwise the communication cycle is ignored and a communication failure is indicated forcing high the spi_err flag. any number of the STGAP1S can be connected in daisy chain, and only 4 lines for the spi and one for the sd are required in order to guarantee access to status and configuration registers of each device. an example of daisy chain configuration is shown in figure 21 . ck sdi sdo cs msb lsb lsb n-1 n-2 msb hiz n-1 n-2 t setcs t ensdo t setsdi t holsdi t vsdo t holsdo t fck t rck t lck t hck t dissdo t holcs t descs msb
docid027190 rev 1 45/70 STGAP1S spi interface 70 figure 21. spi daisy chain connection example in case a bootstrap capacitor and a diode are used to generate the vh supply voltage for the high-side drivers, it is recommended to hav e one dedicated sd line for all of the high- side drivers and another dedicated sd line for all of the low-side drivers. an example of such topology is shown in figure 22 . figure 22. spi daisy chain connection example when bootstrap technique is used for high-side drivers c mosi miso ck device 1 device 2 device n sd sdo ck cs sdi i s o l a t i o n cs sd sd sdo ck cs sdi i s o l a t i o n sd sdo ck cs sdi i s o l a t i o n c mosi miso ck sd sdo ck cs sdi vh vl gndiso i s o l a t i o n vh _hs1 c boot _hs1 sd sdo ck cs sdi vh vl gndiso i s o l a t i o n vh _ls sd sdo ck cs sdi vh vl gndiso i s o l a t i o n vh _hs2 c boot _hs2 sd sdo ck cs sdi vh vl gndiso i s o l a t i o n vh _ls gndiso gndiso sd_hs sd_ls cs
spi interface STGAP1S 46/70 docid027190 rev 1 crc protection all the command and data bytes have to be fo llowed by a crc code. if the crc_spi bit is set high, this code is used to check the data byte is correct, otherwise the crc byte is ignored. in this case the crc byte must be transmitted by the host, but its value is unimportant. a failure on the crc check causes the respec tive data byte is ignored and the spi_err flag is set high. the polynomial generator of the crc code is x 8 + x 2 + x + 1 corresponding to the block diagram in figure 23 . figure 23. block diagram of the crc generator the host must transmit to th e device the inverted crc code computed using the following procedure: ? initialize crc to all 1 ? start the calculation from the most significant bit of the message ? invert the crc result in case of a writereg command, the crc of the data byte (i.e.: the new register value) must be calculated initializing the computation system to the crc of the command byte (i.e.: the crc is calculated on a 16-bit message comp osed by the command + data byte). this way a data byte cannot be accepted as a comma nd byte and vice-versa. some examples are listed in table 11 . the device always transmits a response byte followed by a crc computed using the same polynomial generator (x 8 + x 2 + x + 1). the crc byte transmitted by the device is not inverted. if no response is required, the word returned by the device has no meaning and it should be discarded. some examples are listed in table 12 . x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 message ( from msb to lsb ) table 11. crc byte examples (from host to device) command command byte command crc data byte data crc stopconfig 0x3a 0xaa n.a. n.a. writereg(cfg1, 0x20) 0x8c 0xa1 0x20 0x82 writereg(cfg5, 0x06) 0x99 0xca 0x06 0x66 resetstatus 0xd0 0x32 n.a. n.a. readreg(cfg3) 0xbe 0x3f n.a. n.a.
docid027190 rev 1 47/70 STGAP1S spi interface 70 table 12. crc byte examples (from device to host) data byte data crc 0x00 0xf3 0xea 0x6b 0xf5 0x36 0x2a 0x25
programming manual STGAP1S 48/70 docid027190 rev 1 9 programming manual 9.1 spi commands the commands summary is given in table 13 . 9.1.1 startconfig and stopconfig commands to configure the device it must be switch ed to the configuration mode. when the configuration mode is set, the cfg bit is high, otherwise it is low. to switch the device to the configuration mode the startconfig command must be sent. this command is accepted when the sd line is low only. if the command has been correctly received and interpreted, the ic registers writing is enabled. the sd pin must be kept low during the confi guration. if the sd pin is raised during the configuration procedure the device immediately quits the configuration mode causing a fault table 13. spi commands command mnemonic command value action notes startconfig 0 0 1 0 1 0 1 0 device configuration start enter cfg mode sd low only stopconfig 0 0 1 1 1 0 1 0 device configuration/check completed leave cfg mode sd low only nop 0 0 0 0 0 0 0 0 no operation writereg 1 0 0 a a a a a write aaaaa register cfg mode only readreg 1 0 1 a a a a a read aaaaa register resetreg 1 1 0 a a a a a reset aaaaa register cfg mode only (1) sd low only resetstatus 1 1 0 1 0 0 0 0 reset all the status registers sd low only globalreset 1 1 1 0 1 0 1 0 global reset cfg mode only sleep 1 1 1 1 0 1 0 1 device enters in standby mode sd low only 1. the status1, status2 and status3 can be also reset out of the configuration mode. table 14. startconfig command synopsis byte 1 2 to device 0010 1010 1101 1010 (1) 1. the crc byte of the command, if the crc check is disabled this byte is ignored. table 15. stopconfig command synopsis byte 1 2 to device 0011 1010 1010 1010 (1) 1. the crc byte of the command, if the crc check is disabled this byte is ignored.
docid027190 rev 1 49/70 STGAP1S programming manual 70 error indicated by the regerrl and regerrr bi ts. in this case a ll the changes operated on device configuration are undone and th e previous configuration is restored. at the end of the device setup the stopconfig command has to be sent in order to quit the configuration mode and make all changes effective. 9.1.2 writereg command the device register can be written through the writereg command when the device is set in the configuration mode only (refer to section 9.1.1 ), otherwise the write command is ignored and the spi_err flag is forced low. the writereg command is followed by the data to be written into the target register. the crc code following the data is based on both command and data bytes. in this way, in case of communication error, a data byte cannot be decoded as a command and vice-versa (refer to section : crc protection on page 46 ). 9.1.3 readreg command the registers of the device can be read an ytime through the readreg command. after the command is received and decoded by the device, the register value and the respective crc code is prepared for the transmission. the crc polynomial used by the device during the transmission is different from the one used by the host, but the crc code is not inverted before transmission (refer to section : crc protection ). the time required to obtain the reading result changes according to the side where the register is located. the reading of a local regi ster (low voltage side) is available in 800 ns. the reading of a remote register (isolated side ), if no communication error occurs between the two sides of the device, is available in 30 s. table 16. writereg command synopsis byte1234 to device 100a aaaa (1) 1. the command byte where aaaaa is the address of the target register. cccc cccc (2) 2. the crc byte of the command, if the c rc check is disabled this byte is ignored. dddd dddd (3) 3. data to be written into the target register. kkkk kkkk (4) 4. the crc byte of the command and data, if the crc check is disabled this byte is ignored. table 17. readreg command synopsis byte 1 2 3 (1) 1. proper time have to be waited in order to allow the device to prepare the data. 4 to device 101a aaaa (2) 2. the command byte where aaaaa is the address of the target register. cccc cccc (3) 3. the crc byte of the command, if the crc check is disabled this byte is ignored. 0000 0000 cccc cccc (4) 4. the crc byte of the nop command. from device 0000 0000 0000 0000 dddd dddd (5) 5. data read from the target register. kkkk kkkk (6) 6. the crc byte of the data.
programming manual STGAP1S 50/70 docid027190 rev 1 after the read result is ready, the host microcontroller must send another command in order to receive it. the time required to make the read result available depends on the register type: remote registers need longer time bec ause of the isolated interface communication. 9.1.4 resetreg, resetstatus and globalreset commands the resetreg command has different function accordin g to the type of the target register: when it is a configuration regist er, its value is restored to the default. when it is a status register the respective failure fl ags, if latched, are released. the configuration registers can be reset when the device is in the configuration mode only, otherwise the command is ignored and the spi_err flag is forced low. in both cases (configuration or status regi ster) the command is acce pted only when the sd input is low, otherwise the spi_err flag is forced low. the resetstatus command is a specific reset command which acts on all status registers releasing all the latched flags. the command is executed only when the sd input is low, otherwise the spi_err flag is forced low. the globalreset command reset all the registers to the default and releases all the failure flag (if latched). it can be sent when the device is in the configuration mode only, otherwise the command is ignored and the spi_err flag is forced low. 9.1.5 sleep command table 18. resetreg command synopsis byte 1 2 to device 110a aaaa (1) 1. the command byte where aaaaa is the address of the target register. cccc cccc (2) 2. the crc byte of the command, if the crc check is disabled this byte is ignored. table 19. resetstatus command synopsis byte 1 2 to device 1101 0000 0011 0010 (1) 1. the crc byte of the command, if the crc check is disabled this byte is ignored. table 20. globalreset command synopsis byte 1 2 to device 1110 1010 1001 0100 (1) 1. the crc byte of the command, if the crc check is disabled th is byte is ignored. table 21. sleep command synopsis byte 1 2 to device 1111 0101 1100 1001 (1) 1. the crc byte of the command, if the crc check is disabled this byte is ignored.
docid027190 rev 1 51/70 STGAP1S programming manual 70 the command forces the device to switch in low power consumpt ion mode within a t sleep period. the command is executed only when the sd pin in low, if the sd pin is high the command is ignored and the spi_err flag is forced low. to exit from the sleep mode it is necessary a transition low-to-high on the sd pin. after a t awake time the device is operative. if during the switching between operation and lo w consumption modes the sd pin is raised, the device returns to the operation mode within a t awake time. 9.1.6 nop command the command does not modify the device status and does not generate any answer. 9.2 registers and flags description all device features can be configured through a set of 8-bit long registers. there are three different types of registers: ? local registers are located on the low voltage side ? remote registers are located on the isolated side ? shared registers are located both on the lo w voltage and isolated side and the value of the two copies is kept synchronized. table 22. nop command synopsis byte 1 2 to device 0000 0000 0000 1100 (1) 1. the crc byte of the command, if the crc check is disabled this byte is ignored.
programming manual STGAP1S 52/70 docid027190 rev 1 a map of the user registers is shown in table 23 . 9.2.1 cfg1 register (low voltage side) the cfg1 register has the structure of table 24 . the crc_spi bit enables the crc check on the spi communication protocol. the uvlod_en bit enables the uvlo protection on vdd supply voltage. table 23. registers map name add- ress side (1) structure [7] [6] [5] [4] [3] [2] [1] [0] cfg1 0x0c l crc_spi uvlod_en sd_flag diag_en dtset infilter cfg2 0x1d r senseth desatcur desatth cfg3 0x1e r 2ltoth 2ltotime cfg4 0x1f r ovlo_en uvlolatch vlonth vhonth cfg5 0x19 r 2lto_en clamp_en desat_en sense_en status1 0x02 l ovloh ovlol desat sense uvloh uvlol tsd twn status2 0x01 l regerrr asc gate status3 0x0a l cfg dt_err spi_err regerrl ovlod uvlod test1 0x11 r goffchk gonchk deschk snschk rchk diag1 0x05 l diag1_7 diag1_6 diag1_5 diag1_4 diag1_3 diag1_2 diag1_1 diag1_0 diag2 0x06 l diag2_7 diag2_6 diag2_5 diag2_4 diag2_3 diag2_2 diag2_1 diag2_0 1. r: remote (isolated side), l: local (low voltage side). table 24. cfg1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 crc_spi uvlod_en sd_flag diag_en dtset infilter default/reset 0 0 1 0 00 00 table 25. crc enable crc_spi spi communication protocol crc enable 0 disabled 1 enabled
docid027190 rev 1 53/70 STGAP1S programming manual 70 the sd_flag bit sets the sd pin functionality according to table 27 . when the reset of the failure flags through the sd pin is enabled, keeping low the sd pin for at least t release causes all the latched flags of the status regi sters to be released at next sd rising edge. the diag_en bit sets if the in-/diag2 pin works as the input or open drain output according to table 28 . refer to section 7.1 on page 26 for details. the dtset bits set the deadtime value. the infilter bits set the input deglitch time t deglitch for sd, in- and in+ pins. table 26. vdd supply voltage uvlo enable uvlod_en supply voltage uvlod enable 0 disabled 1 enabled table 27. sd pin fault management sd_flag sd pin functionality 0 sd pin do not reset status registers 1 sd pin reset status registers table 28. in-/diag2 pin functionality diag_en in-/diag2 pin functionality 0 the in-/diag2 pin work as input 1 the in-/diag2 pin work as open drain output table 29. deadtime dtset [1 ... 0] deadtime value [ns] 00disabled 0 1 250 1 0 800 1 1 1200 table 30. input deglitch time infilter [1 ... 0] input deglitch time value [ns] 00disabled 0 1 210 1 0 560 1170
programming manual STGAP1S 54/70 docid027190 rev 1 9.2.2 cfg2 register (isolated side) the cfg2 register has the structure of table 31 . . the senseth bits set the sense comparator threshold according to table 32 . refer to section 7.8 on page 34 for details. the desatcurr parameter sets the current sourced by the desat pin according to table 33 and the desatth parameter sets the desat comparator threshold according to table 34 . refer to section 7.6 on page 31 for details. table 31. cfg2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 senseth desatcur desatth default/reset 000 00 100 table 32. sense threshold senseth [2 ... 0] sense threshold value [mv] 0 0 0 100 0 0 1 125 0 1 0 150 0 1 1 175 1 0 0 200 1 0 1 250 1 1 0 300 1 1 1 400 table 33. desat current desatcur [1 ... 0] desat current value [a] 00250 01500 10750 1 1 1000
docid027190 rev 1 55/70 STGAP1S programming manual 70 9.2.3 cfg3 register (isolated side) the cfg3 register has the structure of table 35 . the 2ltoth parameter sets the voltage value which is actively forced during the 2-level turn- off sequence (refer to section 7.10 on page 34 for details). table 34. desat threshold desatth [2 ... 0] desat threshold value [v] 000 3 001 4 010 5 011 6 100 7 101 8 110 9 111 10 table 35. cfg3 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2ltoth 2ltotime default/reset 0000 0000
programming manual STGAP1S 56/70 docid027190 rev 1 the 2ltotime parameter sets the duration of the 2-level turn-off sequence (refer to section 7.10 on page 34 for details). if the 2ltotime is set to zero, the 2-level turn-off feature is disabled. table 36. 2ltoth 2ltoth [3 ... 0] 2lto threshold value [v] 0000 7.00 0001 7.50 0010 8.00 0011 8.50 0100 9.00 0101 9.50 0110 10.00 0111 10.50 1000 11.00 1001 11.50 1010 12.00 1011 12.50 1100 13.00 1101 13.50 1110 14.00 1111 14.50
docid027190 rev 1 57/70 STGAP1S programming manual 70 9.2.4 cfg4 register (isolated side) the cfg4 register has the structure of table 38 . the ovlo_en bit enables the ovlo protection on the vh and vl power supply according to table 39 . the uvlolatch bit sets if the uvlo is latched or not (refer to section 7.4 on page 30 for details). table 37. 2-level turn-off time value 2ltotime [3 ... 0] 2-level turn-off time value [s] 0000 disabled 0001 0.75 0010 1.00 0011 1.50 0100 2.00 0101 2.50 0110 3.00 0111 3.50 1000 3.75 1001 4.00 1010 4.25 1011 4.50 1100 4.75 1101 5.00 1110 5.25 1111 5.50 table 38. cfg4 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovlo_en uvlolatch vlonth vhonth default/reset 0 0 00 00 table 39. vh and vl supply voltages ovlo enable ovlo_en ovlo supply voltage enable 0 disabled 1 enabled
programming manual STGAP1S 58/70 docid027190 rev 1 the vlonth bits set the uvlo threshold on the negative power supply according to table 41 . setting the parameter to ze ro disables the uvlo protection of the vl supply. the vhonth bits set the uvlo threshold on the positive power supply according to table 42 . setting the parameter to zero disables the uvlo protection of the vh supply. 9.2.5 cfg5 register (isolated side) the cfg4 register has the structure of table 43 . table 40. uvlo protection management uvlolatch uvlo protection management 0 uvlo protection is not latched 1 uvlo protection is latched table 41. vl negative supply voltage uvlo threshold vlonth [1 ... 0] negative supply voltage uvlo threshold [v] 0 0 disabled 01 -3 10 -5 11 -7 table 42. vh positive supply voltage uvlo threshold vhonth [1 ... 0] positive supply voltage uvlo threshold [v] 0 0 disabled 01 10 10 12 11 14 table 43. cfg5 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2lto_en clamp_en desat_en sense_en default/reset 0 1 1 0
docid027190 rev 1 59/70 STGAP1S programming manual 70 the 2lto_en bit sets when the feature takes place according to table 44 . refer to section 7.10 on page 34 for details. the 2ltoth bit sets the 2-level turn-off threshold according to table 36 on page 56 and the 2-level turn-off time according to table 37 . the sense_en bit sets if the sense overcurren t function is enabled or not (refer to section 7.8 on page 34 for details). the desat_en bit sets if the desaturation protection is enabled or not (refer to section 7.6 on page 31 for details). set the clamp_en bit to enable t he miller clamp feature (refer to section 7.9 on page 34 for details). table 44. 2lto mode 2lto_en 2lto mode 0 2lto always active 1 2lto active only after a fault event table 45. sense comparator enabling sense_en sense comparator status 0 sense comparator disabled 1 sense comparator enabled table 46. desat comparator enabling desat_en desat comparator status 0 desat comparator disabled 1 desat comparator enabled table 47. miller clamp feature enabling clamp_en miller clamp feature status 0 miller clamp feature disabled 1 miller clamp feature enabled
programming manual STGAP1S 60/70 docid027190 rev 1 9.2.6 status1 register (low voltage side) the status1 is a read only register that reports some device failure flags. all flags are active high (high value indicates a failure condition). the status1 register has the structure of table 48 . a description of the status1 register bits is provided in table 49 . table 48. status1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovloh ovlol desat sense uvloh uvlol tsd twn default (1) 00 0 0 1000 reset 0 0 0 0 0 0 0 0 1. default value of the local copy of the register. the value will be updated according to the actual information from the isolated side. the default is forced at the device power-up, when the register al l the flags are forced low (no failures). table 49. status1 register description name bit fault latched force ?safe state? note ovloh 7 vh overvoltage flag. it is forced high when vh is over ov vhoff threshold. always yes ovlol 6 vl overvoltage flag. it is forced high when vh is over ov vloff threshold. always yes desat 5 desaturation flag. it is forced high when desat pin voltage reach v desatth threshold. always yes sense 4 sense flag. it is forced high when sense pin voltage reach v senseth threshold. always yes uvloh 3 vh undervoltage flag. it is forced high when vh is below vhoff threshold. when uvlolatch is high only yes if not latched (uvlolatch low) returns high when vh is over vh on threshold. uvlol 2 vl undervoltage flag. it is forced high when vl is over vloff threshold. when uvlolatch is high only yes if not latched (uvlolatch low) returns high when vl is below vlon threshold. tsd 1 thermal shutdown protection flag. it is forced high when overtemperature shutdown threshold is reached. no (hysteresis) yes twn 0 thermal warning flag. it is forced high when overtemperature shutdown threshold is reached. no (hysteresis) no
docid027190 rev 1 61/70 STGAP1S programming manual 70 9.2.7 status2 register (low voltage side) the status2 is a read only register. the status2 register has the structure of table 50 . a description of the status2 register bits is provided in table 51 . 9.2.8 status3 register (low voltage side) the status3 is a read only register. the status3 register has the structure of table 52 . table 50. status2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 regerrr asc gate default (1) 100 reset 0 0 0 1. default value of the local copy of the register. the value will be updated according to the actual information from the isolated side. the default is forced at the device power-up, when the register al l the flags are forced low (no failures). table 51. status2 register description name bit fault latched force ?safe state? note regerrr 2 register or communication error on isolated side. it is forced high when: ? programming procedure is not correctly performed. ? isolated interface communication fails. ? an unexpected register value change occurs in one of the remote registers. it is also latched at power-up/reset and from sleep state. always yes this flag is released when a programming procedure is correctly performed also. asc 1 asc pin status. when asc pin is high the flag reports '1', otherwise is '0'. no no see details in section 7.12 on page 37 gate 0 gate status flag. when gon is active the flag is '1', when goff is active it is '0'. no no table 52. status3 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cfg dt_err spi_err regerrl ovlod uvlod default (1) 00 0 1 0 1 reset 0 0 0 0 0 0 1. the default is forced at the device power-up, when the register all the flags are forced low (no failures).
programming manual STGAP1S 62/70 docid027190 rev 1 a description of the status2 register bits is provided in table 53 . 9.2.9 test1 register (isolated side) the test1 register has the structure of table 54 . setting an one check bit of the register enables the respective check mode. table 53. status3 register description name bit fault latched force ?safe state? note cfg 5 configuration flag. it is high when device is in configuration mode. no no see details in section 9.1.1 on page 48 dt_err 4 deadtime error flag. this bit is forced high when a violation of internal dt is detected. always no see details in section 7.2 on page 27 spi_err 3 spi communication error flag. it is forced high when the spi communication fails cause: ? wrong crc check. ? wrong number of ck rising edges. ? attempt to execute a not-allowed command. attempt to read, writ e or reset at a not- available address. always no regerrl 2 register or communication error on low voltage side. it is forced high when: - ? programming procedure is not correctly performed. ? isolated interface communication fails. ? an unexpected register value change occurs in one of the remote registers. it is latched at power-up/reset also. always yes this flag is released when a programming procedure is correctly performed also. ovlod 1 vdd overvoltage flag. it is forced high when vdd is over ovvddoff threshold. always yes uvlod 0 vdd undervoltage flag. it is forced high when vdd is below vddon threshold. it is latched at power-up/reset also. always yes table 54. test1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 goffchk gonchk deschk snschk rchk default/reset 0 0 0 0 0
docid027190 rev 1 63/70 STGAP1S programming manual 70 9.2.10 diag1 and diag2 registers (low voltage side) the diag1 register has the structure of table 56 . the diag2 register has the structure of table 57 . if a bit in the diag1 register is high, the co rresponding fault events turn on the open drain connected to the diag1 pin forcing the output low. if a bit in the diag2 register is high and th e diag_en bit is high, the corresponding fault events turn on the open drain connected to the diag2 pin forcing the output low. table 55. check mode bit check mode rchk sense resistor snschk sense comparator deschk desat comparator gonchk gon to gate path goffchk goff to gate path table 56. diag1 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 diag1_7 diag1_6 diag1_5 diag1_4 d iag1_3 diag1_2 diag1_1 diag1_0 default/reset11011010 table 57. diag2 register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 diag2_7 diag2_6 diag2_5 diag2_4 diag2_3 diag2_2 diag2_1 diag2_0 default/reset 0 0 0 0 0 0 0 0
programming manual STGAP1S 64/70 docid027190 rev 1 the relation between the diag1 and diag2 regist er bits and failure events is described in table 58 . table 58. relation between diag1/2 bits and failure conditions diag1/2 bit failure status registers bit 0 thermal warning twn 1 thermal shutdown tsd 2 asc feedback asc, dt_err 3 desaturation and sense detection desat, sense 4 overvoltage failure ovloh, ovlol 5 undervoltage failure uvloh, uvlol 6 vdd power supply failure uvlod, ovlod 7 spi communication error or register failure spi_err, regerrl, regerrr
docid027190 rev 1 65/70 STGAP1S typical application diagram 70 10 typical application diagram figure 24. typical application diag ram in half-bridge configuration refer to figure 12 on page 33 in the dedicated section 7.7 on page 32 for the connection of the vceclamp pin. 1k gnd_ hs vh_ hs vl_ hs i s o l a t i o n level shifter floating ground uvlo vh uvlo vl desat vh vregiso gon goff vl clamp gndiso spi sd vdd vreg gnd sdo 3v3 voltage reg gnd desatth desatcurr + 2lvtoth clampth + + ck sdi control logic in+ diag1 sense senseth + in-/diag2 floating section control logic cs c p5v p5v p5v p5v p5v hv_bus gnd_pwr load_phase p5v p5v 1k gnd_ ls vh_ ls vl_ ls i s o l a t i o n level shifter floating ground uvlo vh uvlo vl desat vh vregiso gon goff vl clamp gndiso spi sd vdd vreg gnd sdo 3v3 voltage reg gnd desatth desatcurr + 2lvtoth clampth + + ck sdi control logic in+ diag1 sense senseth + in-/diag2 floating section control logic cs
package information STGAP1S 66/70 docid027190 rev 1 11 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark.
docid027190 rev 1 67/70 STGAP1S package information 70 figure 25. so24w package outline table 59. so24w package mechanical data symbol dimensions (mm) notes min. typ. max. a2.35 2.65 a1 0.10 0.30 b0.33 0.51 c0.23 0.32 d 15.20 15.60 (1) 1. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per side. e7.40 7.60 e1.27 h 10.00 10.65 h0.25 0.75 l0.40 1.27 k 0 8 degrees ddd 0.10
package information STGAP1S 68/70 docid027190 rev 1 figure 26. so24w suggested land pattern
docid027190 rev 1 69/70 STGAP1S ordering information 70 12 ordering information 13 revision history table 60. device summary order code package packing STGAP1S so24w tube STGAP1Str so24w tape and reel table 61. document revision history date revision changes 19-nov-2014 1 initial release.
STGAP1S 70/70 docid027190 rev 1 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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